1. Field of the Invention
This invention relates to a semiconductor device, and more particularly to bump electrodes formed on the semiconductor device and a method for manufacturing the semiconductor device.
2. Description of the Related Art
Recently, the thickness of a large-scale semiconductor integrated circuit (LSI) has been reduced and a large number of electrodes are disposed with the pitch between electrodes reduced. This type of LSI is widely used in a logic circuit having a large number of signal terminals.
Further, as the mounting technique is further enhanced, the technique called the tape automated bonding (TAB) technique is more widely used. The TAB technique is used to previously form bump electrodes which project high in the signal derive-out portion of the LSI chip and previously prepare a film carrier. The film carrier is formed by forming a lead pattern of copper or the like on a film having a high insulating property and high heat resistance. When the LSI chip is bonded to the lead pattern of the film carrier, the inner leads of the lead pattern formed on the film carrier are first aligned with the bump electrodes, and then, the front end portions of the inner leads are pressed against the bump electrodes and they are heated so as to be bonded together.
FIG. 10 shows an example of the structure of the conventional bump electrode.
A pad 82 is formed of aluminum on a semiconductor substrate 81. A passivation film 83 is formed on the pad 82 and substrate 81 and an opening 84 is formed in the passivation film 83 to expose part of the surface of the pad 82. A barrier metal layer 86 is formed on the bottom and side surfaces of the opening 84 and that portion of the passivation film 83 which lies on the peripheral portion of the opening 84 and a bump electrode 85 is formed on the barrier metal layer 86. Generally, gold (Au) is used to form the bump electrode 85 and the barrier metal layer 86 prevents formation of a weak chemical composite by forming the gold layer in direct contact with the pad 82. The bump electrode 85 is electrically connected to the pad 82 via the barrier metal layer 86.
With formation of LSIs of greater miniaturization, it becomes necessary to reduce the pitch between the pads and reduce the pad size. Therefore, the size of the bump electrode 85 becomes small so that the area of that portion of the bump electrode 85 which is set in contact with the inner lead will be decreased, thereby making it difficult to sufficiently enhance the strength of bonding therebetween. In addition, when the LSI chip is bonded to the inner lead of the film carrier, the front end portion of the inner lead tends to be deviated from the bump electrode 85 and the contact area therebetween is further decreased, thereby causing a serious problem that the bonding strength thereof will be further lowered.
As one example of a method for solving the above problem. It is considered to form the bump electrode with the area of the upper portion thereof made larger than that of the bottom portion thereof so as to increase the contact area with the inner lead.
That is, as shown in FIGS. 11A, 11B, the pad 82 and passivation film 83 are formed on the substrate 81 and a photoresist film 91 is formed to cover them. Then, an opening 94 is formed in the bump electrode forming position by subjecting the photoresist film 91 to the exposure, development and baking. In this case, the cross section of the opening 94 is made such that the area of the upper portion thereof will be larger than that of the bottom portion thereof by controlling the condition of the exposure, development and baking. Next, gold is plated on the inner wall of the opening 94 with the photoresist film 91 used as a mask so as to form a bump electrode 95. After this, as shown in FIG. 11B, the photoresist film 91 is removed.
In the bump electrode 95 of the above structure, the area of the upper portion thereof can be made larger than that of the bottom portion. However, in the above manufacturing method, since the upper portion of the bump electrode 95 spreads in all directions, the distance between the adjacent bump electrodes is reduced. Therefore, if the specification of the pad interval is set to be small, there occurs a possibility that the adjacent bump electrodes may be set in contact with each other.
FIG. 12 shows another example of a method for solving the above problem. In this case, the plane pattern of the bump electrodes 100 is made such that the length of the bump electrode in the arrangement direction of the bump electrodes will be made smaller than that in the direction perpendicular to the arrangement direction. Therefore, a sufficiently large distance can be set between the adjacent bump electrodes 100 and it becomes possible to prevent the bump electrodes 100 from being set in contact with each other. However, in order to form the bump electrode 100 of the above structure, it is also necessary to form the pads such that the length of the pad in the arrangement direction will be made smaller than that in the direction perpendicular to the arrangement direction. Therefore, the area of an LSI chip 101 in which the pads and bump electrodes are arranged becomes larger and the whole size of the LSI chip is increased. The structure in which the length of the bump electrode in the arrangement direction of the bump electrodes is made smaller than that in the direction perpendicular to the arrangement direction is disclosed in Jpn. Pat. Appln. KOKAI Publication No. 2-28933 and No. 2-119228.